TY - GEN
T1 - A Model-Driven Architecture Approach to Accelerate Software Code Generation
AU - Bhadra, Mayuri
AU - Lopera, Daniela Sanchez
AU - Kunzelmann, Robert
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In the evolving domain of embedded programming, languages like Rust are gaining importance alongside the traditionally dominant C language. This highlights the need for different coding styles to achieve the same functionality due to the various challenges posed by different programming languages, subsets of language constructs, run time systems, CPU architectures, and hardware peripherals. It results in the manual creation of multiple code variants, leading to code duplication, and introducing laborious and error-prone processes. This paper introduces a model-based code generator aligned with the ModelDriven Architecture (MDA) that leverages software models. The proposed generator can be applied in the neural network (NN) domain, generating low-level driver code for NN primitives across various hardware devices, showcasing the adaptability of our approach. In this work, we specifically concentrate on core tensor math operators, the foundational elements of NN primitives, with emphasis on both RISC-V and standard CPU architectures. Using metamodeling, it creates unique configurations for each operator in the target code, offering an efficient and coherent alternative to manual coding. Our experimental results show a reduction of approximately a factor of 62, on average, in Source Lines of Code (SLoC) when employing our Model-Driven approach, as opposed to the SLoC generated for all variants when manually coded. This highlights the efficiency of our proposed solution by reducing the overall development effort and enhancing the efficiency of embedded software development.
AB - In the evolving domain of embedded programming, languages like Rust are gaining importance alongside the traditionally dominant C language. This highlights the need for different coding styles to achieve the same functionality due to the various challenges posed by different programming languages, subsets of language constructs, run time systems, CPU architectures, and hardware peripherals. It results in the manual creation of multiple code variants, leading to code duplication, and introducing laborious and error-prone processes. This paper introduces a model-based code generator aligned with the ModelDriven Architecture (MDA) that leverages software models. The proposed generator can be applied in the neural network (NN) domain, generating low-level driver code for NN primitives across various hardware devices, showcasing the adaptability of our approach. In this work, we specifically concentrate on core tensor math operators, the foundational elements of NN primitives, with emphasis on both RISC-V and standard CPU architectures. Using metamodeling, it creates unique configurations for each operator in the target code, offering an efficient and coherent alternative to manual coding. Our experimental results show a reduction of approximately a factor of 62, on average, in Source Lines of Code (SLoC) when employing our Model-Driven approach, as opposed to the SLoC generated for all variants when manually coded. This highlights the efficiency of our proposed solution by reducing the overall development effort and enhancing the efficiency of embedded software development.
KW - Code Generation
KW - metamodeling
KW - model-driven architecture
KW - model-of-software
UR - http://www.scopus.com/inward/record.url?scp=85201951196&partnerID=8YFLogxK
U2 - 10.1109/ICoSSE62619.2024.00012
DO - 10.1109/ICoSSE62619.2024.00012
M3 - Conference contribution
AN - SCOPUS:85201951196
T3 - Proceedings - 2024 7th International Conference on Software and System Engineering, ICoSSE 2024
SP - 23
EP - 30
BT - Proceedings - 2024 7th International Conference on Software and System Engineering, ICoSSE 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Conference on Software and System Engineering, ICoSSE 2024
Y2 - 19 April 2024 through 21 April 2024
ER -