A method for phase noise analysis of RF circuits

Dimo Martev, Sven Hampel, Ulf Schlichtmann

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

1 Zitat (Scopus)

Abstract

In this paper we present a method for analysis of phase noise in logic circuits. This method alLows the design and verification of phase noise critical circuits using a digital toolchain, significantly reducing the design time and effort compared to the traditional approach using analog tools such as SPICE simulation. It is based on a set of pre-characterized standard cells and the generated phase noise is estimated using a lookup table approach. Comparison of the estimation results with back-annotated analog simulations in 28 nm CMOS technology show that the error of the estimation is within 7.2% of the actual phase noise, and the runtime is reduced by three orders of magnitude.

OriginalspracheEnglisch
TitelGLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
Herausgeber (Verlag)Association for Computing Machinery
Seiten227-231
Seitenumfang5
ISBN (elektronisch)9781450349727
DOIs
PublikationsstatusVeröffentlicht - 10 Mai 2017
Veranstaltung27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Kanada
Dauer: 10 Mai 201712 Mai 2017

Publikationsreihe

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
BandPart F127756

Konferenz

Konferenz27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Land/GebietKanada
OrtBanff
Zeitraum10/05/1712/05/17

Fingerprint

Untersuchen Sie die Forschungsthemen von „A method for phase noise analysis of RF circuits“. Zusammen bilden sie einen einzigartigen Fingerprint.

Dieses zitieren