TY - GEN
T1 - A framework that enables systematic analysis of mixed-signal applications on FPGA
AU - Rutsch, Gabriel
AU - Groebner, Maximilian
AU - Sanders, Anthony
AU - Maier, Konrad
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - We present a framework that enables systematic analysis of mixed-signal application on FPGA and show its application during architecture validation of a power controller. The open source synthesizable model generator for mixed-signal blocks (msdsl) is used to create a synthesizable prototype of the analog power control application. A library of instrumentation elements enables control from a host computer, time control, analog event capture, analog stimulus and noise generation, as well as trace, read and write of arbitrary signals. This keeps the effort of building the FPGA application prototype low and provides good debugging and analysis capabilities. The end-result is a unique analysis framework for mixed-signal applications that offers almost real time analog simulation speed - thus considering software as well as analog and digital hardware - no risk of damaging equipment and simulator alike analysis and debugging capabilities at a low overhead through an instrumentation library.
AB - We present a framework that enables systematic analysis of mixed-signal application on FPGA and show its application during architecture validation of a power controller. The open source synthesizable model generator for mixed-signal blocks (msdsl) is used to create a synthesizable prototype of the analog power control application. A library of instrumentation elements enables control from a host computer, time control, analog event capture, analog stimulus and noise generation, as well as trace, read and write of arbitrary signals. This keeps the effort of building the FPGA application prototype low and provides good debugging and analysis capabilities. The end-result is a unique analysis framework for mixed-signal applications that offers almost real time analog simulation speed - thus considering software as well as analog and digital hardware - no risk of damaging equipment and simulator alike analysis and debugging capabilities at a low overhead through an instrumentation library.
KW - FPGA
KW - hardware emulation
KW - mixed-signal application analysis
KW - mixed-signal emulation
KW - product validation
UR - http://www.scopus.com/inward/record.url?scp=85149319026&partnerID=8YFLogxK
U2 - 10.1109/RSP57251.2022.10039031
DO - 10.1109/RSP57251.2022.10039031
M3 - Conference contribution
AN - SCOPUS:85149319026
T3 - Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
SP - 50
EP - 56
BT - Proceedings of the 2022 33rd IEEE International Workshop on Rapid System Prototyping
PB - IEEE Computer Society
T2 - 33rd IEEE International Workshop on Rapid System Prototyping, RSP 2022
Y2 - 13 October 2022
ER -