A Dynamic Priority-aware Coherent Cache Architecture for Reactive Real-Time System

Achieving predictability and performance for real-time workloads on modern multi-processors System-on-Chips is challenging. In particular, their complex hierarchy of caches leads to hard-to-predict memory interactions among concurrently executing tasks and, in turn, to unexpected system overloads. Traditionally, such overloads have been handled by either guaranteeing some level of service - statically or via fair cache and interconnect access - for critical cores or by reacting to overloads by allocating more resources to critical cores and tasks. To our knowledge, dynamically prioritizing accesses of specific cores to memory or improving core-to-core traffic according to software-defined policies have been mostly unexplored directions. This article introduces DyPACC, a hardware design and implementation of a coherent cache that can favor the core-to-memory and core-to-core traffic according to software-defined runtime re-configurable priorities. The proposed cache architecture is implemented directly at the Register Transfer Level using a Hardware Description Language and integrated within an open-source RISC-V SoC framework. Our experimental evaluation of an FPGA-based prototype shows that DyPACC successfully manages bandwidth and latency according to the set priorities with extremely low overhead in terms of hardware resources.