Abstract
We present a comparison of 6T and 8T SRAM design spaces for low-power 65 nm and 45 nm CMOS technologies based on simulations using a multi-objective optimization framework. The influence of a bit-line column multiplexer (MUX) on the 8T design space is shown. We demonstrate that 6T and 8T cells show differing area scaling behavior across the whole design space. We identify points on the area-performance trade-off curves that bound regions where either 6T or 8T SRAM cells are optimal.
Originalsprache | Englisch |
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Seiten (von - bis) | 116-125 |
Seitenumfang | 10 |
Fachzeitschrift | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
Jahrgang | 5349 LNCS |
DOIs | |
Publikationsstatus | Veröffentlicht - 2009 |
Veranstaltung | 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal Dauer: 10 Sept. 2008 → 12 Sept. 2008 |