Abstract
Using an unmodified 130-nm CMOS process, we present the design of an integrated 2-D CMOS stress sensor and trim methodology resulting in 11-bit resolution and 66-dB dynamic range. The n-well-only primary sensing elements and p-Type auxiliary elements allow post-calibrated measurement of both stress magnitude and angle over the commercial temperature range from 5 °C to 90 °C. The implementation is robust to process variation, requires 357 \mu \text{W} when active, and is optimized for duty cycling to reduce system energy consumption.
Originalsprache | Englisch |
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Aufsatznummer | 8984225 |
Seiten (von - bis) | 846-855 |
Seitenumfang | 10 |
Fachzeitschrift | IEEE Journal of Solid-State Circuits |
Jahrgang | 55 |
Ausgabenummer | 4 |
DOIs | |
Publikationsstatus | Veröffentlicht - Apr. 2020 |