A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Junjie Kong; Stephan Henzler; Doris Schmitt-Landsiedel; Liter Siek

doi:10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Junjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek

Medicine and Health

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

3 Zitate (Scopus)

Abstract

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

Originalsprache	Englisch
Titel	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Herausgeber (Verlag)	Institute of Electrical and Electronics Engineers Inc.
Seiten	348-351
Seitenumfang	4
ISBN (elektronisch)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7803972
Publikationsstatus	Veröffentlicht - 3 Jan. 2017
Veranstaltung	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Südkorea Dauer: 25 Okt. 2016 → 28 Okt. 2016

Publikationsreihe

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Konferenz

Konferenz	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Land/Gebiet	Südkorea
Ort	Jeju
Zeitraum	25/10/16 → 28/10/16

Zugriff auf Dokument

10.1109/APCCAS.2016.7803972

Andere Dateien und Links

Verknüpfung zur Publikation in Scopus

Dieses zitieren

Kong, J., Henzler, S., Schmitt-Landsiedel, D., & Siek, L. (2017). A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (S. 348-351). Artikel 7803972 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803972

Kong, Junjie ; Henzler, Stephan ; Schmitt-Landsiedel, Doris et al. / A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. S. 348-351 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

@inproceedings{1c082c3884c844cebacb7032c8daa437,

title = "A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC",

abstract = "This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.",

keywords = "Time-to-digital Converter (TDC), body-biasing, time-mode ADC, two-step architecture, vernier TDC",

author = "Junjie Kong and Stephan Henzler and Doris Schmitt-Landsiedel and Liter Siek",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 ; Conference date: 25-10-2016 Through 28-10-2016",

year = "2017",

month = jan,

day = "3",

doi = "10.1109/APCCAS.2016.7803972",

language = "English",

series = "2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "348--351",

booktitle = "2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016",

}

Kong, J, Henzler, S, Schmitt-Landsiedel, D & Siek, L 2017, A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803972, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., S. 348-351, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Südkorea, 25/10/16. https://doi.org/10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. / Kong, Junjie; Henzler, Stephan; Schmitt-Landsiedel, Doris et al.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. S. 348-351 7803972 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

TY - GEN

T1 - A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

AU - Kong, Junjie

AU - Henzler, Stephan

AU - Schmitt-Landsiedel, Doris

AU - Siek, Liter

PY - 2017/1/3

Y1 - 2017/1/3

N2 - This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

AB - This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

KW - Time-to-digital Converter (TDC)

KW - body-biasing

KW - time-mode ADC

KW - two-step architecture

KW - vernier TDC

UR - http://www.scopus.com/inward/record.url?scp=85011110684&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2016.7803972

DO - 10.1109/APCCAS.2016.7803972

M3 - Conference contribution

AN - SCOPUS:85011110684

T3 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

SP - 348

EP - 351

BT - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Y2 - 25 October 2016 through 28 October 2016

ER -

Kong J, Henzler S, Schmitt-Landsiedel D, Siek L. A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. S. 348-351. 7803972. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). doi: 10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Abstract

Publikationsreihe

Konferenz

Zugriff auf Dokument

Andere Dateien und Links

Fingerprint

Dieses zitieren