Kein Foto von Wolfgang Ecker

Scopus-Profil ansehen

Wolfgang Ecker

Prof. Dr.-Ing.

1992 …2024

Publikationen pro Jahr

Filter
Konferenzbeitrag

Suchergebnisse

  • 2019

    Towards a Python-Based One Language Ecosystem for Embedded Systems Automation

    Han, Z., Devarajegowda, K., Werner, M. & Ecker, W., Okt. 2019, 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. Nurmi, J., Ellervee, P., Halonen, K. & Roning, J. (Hrsg.). Institute of Electrical and Electronics Engineers Inc., 8906949. (2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    9 Zitate (Scopus)
  • 2018

    A machine learning approach for area prediction of hardware designs from abstract specifications

    Zennaro, E., Servadei, L., Devarajegowda, K. & Ecker, W., 12 Okt. 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Konofaos, N., Novotny, M. & Skavhaug, A. (Hrsg.). Institute of Electrical and Electronics Engineers Inc., S. 413-420 8 S. 8491847. (Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    17 Zitate (Scopus)

  • Analog fault simulation automation at schematic level with random sampling techniques

    Wu, L., Hussain, M. K., Abughannam, S., Muller, W., Scheytt, C. & Ecker, W., 29 Mai 2018, Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018. Institute of Electrical and Electronics Engineers Inc., S. 1-4 4 S. (Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    3 Zitate (Scopus)

  • Meta-model Based Automation of Properties for Pre-Silicon Verification

    Devarajegowda, K. & Ecker, W., 2 Juli 2018, Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018. IEEE Computer Society, S. 231-236 6 S. 8644957. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Band 2018-October).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    14 Zitate (Scopus)
  • 2017

    Digital hardware design based on metamodels and model transformations

    Schreiner, J. & Ecker, W., 2017, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Reis, R., Hollstein, T., Raik, J., Kostin, S., Tsertov, A. & O’Connor, I. (Hrsg.). Springer New York LLC, S. 83-107 25 S. (IFIP Advances in Information and Communication Technology; Band 508).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    Open Access
    9 Zitate (Scopus)

  • Earth mover’s distance as a comparison metric for analog behavior

    Rath, A. W., Simon, S., Esen, V. & Ecker, W., 2017, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Reis, R., Hollstein, T., Raik, J., Kostin, S., Tsertov, A. & O’Connor, I. (Hrsg.). Springer New York LLC, S. 173-191 19 S. (IFIP Advances in Information and Communication Technology; Band 508).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    Open Access

  • On generation of properties from specification

    Devarajegowda, K. & Ecker, W., 5 Dez. 2017, 2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017. Institute of Electrical and Electronics Engineers Inc., S. 95-98 4 S. (2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017; Band 2017-January).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    5 Zitate (Scopus)

  • Python based framework for HDSLs with an underlying formal semantics: (Invited paper)

    Devarajegowda, K., Schreiner, J., Findenig, R. & Ecker, W., 13 Dez. 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., S. 1019-1025 7 S. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Band 2017-November).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    12 Zitate (Scopus)

  • The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping

    Mueller-Gritschneder, D., Devarajegowda, K., DIttrich, M., Ecker, W., Greim, M. & Schlichtmann, U., 19 Okt. 2017, Proceedings of the 2017 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017. IEEE Computer Society, S. 79-84 6 S. (Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    18 Zitate (Scopus)
  • 2016

    Automatically comparing analog behavior using Earth Mover's Distance

    Rath, A. W., Simon, S., Esen, V. & Ecker, W., 22 Nov. 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753556. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • Design centric modeling of digital hardware

    Schreiner, J., Findenigy, R. & Ecker, W., 17 Nov. 2016, 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016. Institute of Electrical and Electronics Engineers Inc., S. 46-52 7 S. 7748254. (2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    30 Zitate (Scopus)

  • Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation

    Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T. & Novello, C., 26 Okt. 2016, Proceedings - 19th Euromicro Conference on Digital System Design, DSD 2016. Kitsos, P. (Hrsg.). Institute of Electrical and Electronics Engineers Inc., S. 364-371 8 S. 7723575. (Proceedings - 19th Euromicro Conference on Digital System Design, DSD 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    2 Zitate (Scopus)

  • Efficient handling of the fault space in functional safety analysis utilizing formal methods

    Bernardini, A., Ecker, W. & Schlichtmann, U., 22 Nov. 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753546. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    2 Zitate (Scopus)

  • Fault-effect analysis on system-level hardware modeling using virtual prototypes

    Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T. & Novello, C., 2 Juli 2016, FDL 2016 - 2016 Forum on Specification and Design Languages, Proceedings. IEEE Computer Society, 7880368. (Forum on Specification and Design Languages; Band 0).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    10 Zitate (Scopus)

  • Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study

    Abughannam, S., Wu, L., Mueller, W., Scheytt, C., Ecker, W. & Novello, C., 2016, ANALOG 2016 - 15. ITG/GMM-Fachtagung. VDE VERLAG GMBH, S. 75-80 6 S. (ANALOG 2016 - 15. ITG/GMM-Fachtagung).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    2 Zitate (Scopus)

  • Gate-level-accurate fault-effect analysis at virtual-prototype speed

    Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T. & Novello, C., 2016, Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings. Guiochet, J., Schoitsch, E., Bitsch, F. & Skavhaug, A. (Hrsg.). Springer Verlag, S. 144-156 13 S. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 9923 LNCS).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators

    Ecker, W. & Schreiner, J., 22 Nov. 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753576. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    18 Zitate (Scopus)

  • Speeding up safety verification by fault abstraction and simulation to transaction level

    Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T. & Novello, C., 22 Nov. 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753547. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    6 Zitate (Scopus)

  • Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes

    Chaari, M., Ecker, W., Kruse, T., Novello, C. & Tabacaru, B. A., 22 Sept. 2016, Proceedings - 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN-W 2016. Institute of Electrical and Electronics Engineers Inc., S. 226-229 4 S. 7575382. (Proceedings - 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN-W 2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    5 Zitate (Scopus)

  • Where formal verification can help in functional safety analysis

    Bernardini, A., Ecker, W. & Schlichtmann, U., 7 Nov. 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016. Institute of Electrical and Electronics Engineers Inc., 2980087. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Band 07-10-November-2016).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    13 Zitate (Scopus)
  • 2015

    A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems

    Chaari, M., Ecker, W., Novello, C., Tabacaru, B. A. & Kruse, T., 24 Juli 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015. Institute of Electrical and Electronics Engineers Inc., 7167184. (Proceedings - Design Automation Conference; Band 2015-July).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    7 Zitate (Scopus)

  • The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems

    Bringmann, O., Ecker, W., Gerstlauer, A., Goyal, A., Mueller-Gritschneder, D., Sasidharan, P. & Singh, S., 22 Apr. 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., S. 1698-1707 10 S. 7092666. (Proceedings -Design, Automation and Test in Europe, DATE; Band 2015-April).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    49 Zitate (Scopus)
  • 2014

    A transaction-oriented UVM-based library for verification of analog behavior

    Rath, A. W., Esen, V. & Ecker, W., 2014, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. S. 806-811 6 S. 6742989. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    9 Zitate (Scopus)

  • Metasynthesis for designing automotive socs

    Ecker, W., Velten, M., Zafari, L. & Goyal, A., 2014, DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2602974. (Proceedings - Design Automation Conference).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    6 Zitate (Scopus)

  • Safety evaluation of automotive electronics using virtual prototypes: State of the art and research challeng

    Oetjens, J. H., Bannow, N., Becker, M., Bringmann, O., Burger, A., Chaari, M., Chakraborty, S., Drechsler, R., Ecker, W., Grüttner, K., Kruse, T., Kuznik, C., Le, H. M., Mauderer, A., Müller, W., Müller-Gritschneder, D., Poppen, F., Post, H., Reiter, S. & Rosenstiel, W. &5 mehr, Roth, S., Schlichtmann, U., Schwerin, A. V., Tabacaru, B. A. & Viehl, A., 2014, DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2602976. (Proceedings - Design Automation Conference).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    39 Zitate (Scopus)

  • The metamodeling approach to system level synthesis

    Ecker, W., Velten, M., Zafari, L. & Goyal, A., 2014, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800525. (Proceedings -Design, Automation and Test in Europe, DATE).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    15 Zitate (Scopus)
  • 2013

    Comparison of analog transactions using statistics

    Rath, A. W., Esen, V. & Ecker, W., 2013, 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings. IEEE Computer Society, 6675282. (2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • The semantic of the power intent format UPF: Consistent power modeling from system level to implementation

    Karmann, J. & Ecker, W., 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013. IEEE Computer Society, S. 45-50 6 S. 6662154. (2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    19 Zitate (Scopus)

  • Transaction-level modeling and refinement using state charts

    Findenig, R., Leitner, T. & Ecker, W., 2013, Computer Aided Systems Theory, EUROCAST 2013 - 14th International Conference, Revised Selected Papers. PART 1 Aufl. Springer Verlag, S. 134-141 8 S. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 8111 LNCS, Nr. PART 1).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • 2012

    Single-source hardware modeling of different abstraction levels with state charts

    Findenig, R., Leitner, T. & Ecker, W., 2012, 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012. S. 41-48 8 S. 6418241. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • SystemC as completing pillar in industrial OVM based verification environments

    Ecker, W., Esen, V., Velten, M. & Timisescu, T., 2012, CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK. S. 307-311 5 S. (CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • Testbenches for advanced TLM verification

    Mueller, W. & Ecker, W., 2012, CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK. S. 305 1 S. (CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • The System Verification Methodology for advanced TLM verification

    Oliveira, M. F. S., Haedicke, F., Drechsler, R., Kuznik, C., Le, H. M., Ecker, W., Mueller, W., Große, D. & Esen, V., 2012, CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK. S. 313-322 10 S. (CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    Open Access
    17 Zitate (Scopus)
  • 2011

    Analog transaction level modeling

    Rath, A. W., Esen, V. & Ecker, W., 2011, 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT'11. S. 82 1 S. 6114171. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • 2010

    Fast and accurate UML state chart modeling using TLM+ control flow abstraction

    Findenig, R., Leitner, T., Velten, M. & Ecker, W., 2010, HLDVT'10 - IEEE International High Level Design Validation and Test Workshop, Conference Proceedings. S. 97-102 6 S. 5496654. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • Model reduction techniques for the formal verification of hardware dependent software

    Ecker, W., Esen, V., Findenig, R., Steininger, T. & Velten, M., 2010, HLDVT'10 - IEEE International High Level Design Validation and Test Workshop, Conference Proceedings. S. 148-153 6 S. 5496647. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    2 Zitate (Scopus)

  • State chart refinement validation from approximately timed to cycle callable models

    Findenig, R. & Ecker, W., 2010, 2010 International Symposium on System-on-Chip Proceedings, SoC 2010. S. 72-75 4 S. 5625551. (2010 International Symposium on System-on-Chip Proceedings, SoC 2010).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • TLM+ modeling of embedded HW/SW systems

    Ecker, W., Esen, V., Schwencker, R., Steininger, T. & Velten, M., 2010, DATE 10 - Design, Automation and Test in Europe. Institute of Electrical and Electronics Engineers Inc., S. 75-80 6 S. 5457234. (Proceedings -Design, Automation and Test in Europe, DATE).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    13 Zitate (Scopus)
  • 2009

    Using a dataflow abstracted virtual prototype for HdS-design

    Ecker, W., Heinen, S. & Velten, M., 2009, Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. S. 293-300 8 S. 4796496. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    8 Zitate (Scopus)
  • 2008

    Industrial IP integration flows based on IP-XACT™ standards

    Kruijtzer, W., Van Der Wolf, P., De Kock, E., Stuyt, J., Ecker, W., Mayer, A., Hustin, S., Amerijckx, C., De Paoli, S. & Vaumorin, E., 2008, Design, Automation and Test in Europe, DATE 2008. S. 32-37 6 S. 4484656. (Proceedings -Design, Automation and Test in Europe, DATE).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    43 Zitate (Scopus)
  • 2007

    Impact of description language, abstraction layer, and value representation on simulation performance

    Ecker, W., Esen, V., Schönberg, L., Steininger, T., Velten, M. & Hull, M., 2007, Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. S. 767-772 6 S. 4211893. (Proceedings -Design, Automation and Test in Europe, DATE).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    14 Zitate (Scopus)

  • Implementation of a transaction level assertion framework in systemC

    Ecker, W., Esen, V., Steininger, T., Velten, M. & Hull, M., 2007, Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. S. 894-899 6 S. 4211916. (Proceedings -Design, Automation and Test in Europe, DATE).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    45 Zitate (Scopus)
  • 2006

    Execution semantics and formalisms for multi-abstraction TLM assertions

    Ecker, W., Esen, V., Steininger, T., Velten, M. & Hull, M., 2006, Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06. IEEE Computer Society, S. 93-102 10 S. 1695910. (Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    19 Zitate (Scopus)

  • Specification language for transaction level assertions

    Ecker, W., Esen, V., Steininger, T., Velten, M. & Hull, M., 2006, Proceedings - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06. S. 77-84 8 S. 4110066. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    14 Zitate (Scopus)
  • 2005

    Evolution of paradigm shifts in the automated design process of digital circuits

    Ecker, W. & Schrader, L., 2005, INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). S. 313 1 S. (INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI); Band 1).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • 2004

    Memory models for the formal verification of assembler code using bounded model checking

    Ecker, W., Esen, V., Steininger, T. & Zambaldi, M., 2004, Proceedings - Seventh IEEE International Symposium on Object-Oriented Real-Time Distributed Computing. Gustafsson, J., Aoki, T. & Lee, I. (Hrsg.). S. 129-135 7 S. (Proceedings - Seventh IEEE International Symposium on Object-Oriented Real-Time Distributed Computing).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    3 Zitate (Scopus)
  • 2003

    An approach for mixed coarse-granular and fine-granular re-configurable architectures

    Henftling, R., Ecker, W., Zinn, A., Zambaldi, M. & Bauer, M., 2003, Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 1213346. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

  • Tutorial (T-3) accelerated testbenches

    Ecker, W. & Henftling, R., 2003, ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. Tang, T.-A., Li, W. & Yu, H. (Hrsg.). Institute of Electrical and Electronics Engineers Inc., S. 11 1 S. 05733667. (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Band 1).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)
  • 2000

    A JAVA-based mixed-signal design environment

    Mades, J., Schneider, T., Glesner, M., Windisch, A. & Ecker, W., 2000, Proceedings - 13th Symposium on Integrated Circuits and Systems Design. Reis, R., Van Noije, W. & Monteiro, J. C. (Hrsg.). Institute of Electrical and Electronics Engineers Inc., S. 301-306 6 S. 876046. (Proceedings - 13th Symposium on Integrated Circuits and Systems Design).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    1 Zitat (Scopus)

  • An open VHDL-AMS simulation framework

    Schneider, T., Mades, J., Glesner, M., Windisch, A. & Ecker, W., 2000, 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation. S. 89-94 6 S. (2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation).

    Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

    5 Zitate (Scopus)